1. Field of the Invention
The present invention relates to the stacking and interconnection of leadless chip carriers (LCCs) containing integrated circuit chips (ICs) to achieve, for example, an increased memory capacity in a memory circuit.
2. Description of Related Art
Known memory circuit systems are provided with several printed circuit boards (PCBs), each having a plurality of ICs encapsulated within associated chip packages which are arranged in a single level (not stacked) on the surface of the PCBs. Generally, the PCBs are arranged in a parallel relationship, with each PCB disposed adjacent to and spaced from the other PCBs. Typically, each PCB is spaced by a distance of about 1/2 inch from any adjacent PCBs or other components. As a result, a relatively large amount of space is required for large capacity memory systems. Furthermore, much space between adjacent PCBs, or between PCBs and other components, is left unused.
The known memory circuit systems described above exhibit the disadvantage of taking up a relatively large amount of space, much of which is unused and, thus wasted. Such memory systems, as described above, also exhibit the disadvantage of a limited memory capacity when employed in devices having a limited amount of space available for memory. For example, many conventional computer systems are provided with a housing structure in which a limited amount of space is provided for the memory circuit system. Since the number of PCBs comprising the memory circuit system is limited by the size of the space provided therefor, the memory capacity of these memory systems is also limited by such space constraints. That is, the memory capacity of such computer systems has heretofore been greatly dependent upon and limited by the size of the space reserved for the memory circuit PCBs.